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Altera_Forum
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14 years ago

altsyncram in simple dual-port mode

Hi, the altsyncram in simple dual-port mode does not seem to work correctly. It appears to have some internal pipelining on the data and address inputs relative to the wren and even each other. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

signaltap is correct, data will have latency of one clock at least as address is registered apparently.

Modelsim is showing same latency but your clocking is different.