altsyncram in simple dual-port mode

Thank you, Dave.

Please see my new update which I think contains the information you mentioned.

I am also adding the following design file info...and yes, it is AHDL!

:-) ...but the megafunction IP is transparent to the HDL, of course.

Thanks...here's the relevant code:

INCLUDE "altsyncram.inc";

constant TRADE_DAYS_MAX = 60;

TradeDays_Store : altsyncram WITH (

ADDRESS_ACLR_B = "NONE",

ADDRESS_REG_B = "CLOCK0",

CLOCK_ENABLE_INPUT_A = "BYPASS",

CLOCK_ENABLE_INPUT_B = "BYPASS",

CLOCK_ENABLE_OUTPUT_B = "BYPASS",

INTENDED_DEVICE_FAMILY = "Stratix III",

LPM_TYPE = "altsyncram",

NUMWORDS_A = 2^(log2(TRADE_DAYS_MAX)),

NUMWORDS_B = 2^(log2(TRADE_DAYS_MAX)),

OPERATION_MODE = "DUAL_PORT",

OUTDATA_ACLR_B = "NONE",

OUTDATA_REG_B = "UNREGISTERED",--"CLOCK0",

POWER_UP_UNINITIALIZED = "FALSE",

--RAM_BLOCK_TYPE = "M144K",

READ_DURING_WRITE_MODE_MIXED_PORTS = "DONT_CARE",

WIDTHAD_A = log2(TRADE_DAYS_MAX),

WIDTHAD_B = log2(TRADE_DAYS_MAX),

WIDTH_A = 256,

WIDTH_B = 256,

WIDTH_BYTEENA_A = 1

);

TradeDays_Store.clock0 = clk0;

TradeDays_Store.data_a[] = data_stock_data_in[];

TradeDays_Store.address_a[] = TDS_wrAddress[];

TradeDays_Store.wren_a = TDS_wren;

TradeDays_Store.address_b[] = TDS_rdAddress[];

data_stock_data_out[] = TradeDays_Store.q_b[];