ALTREMOTE_UPDATE error conditions

Hi,

I am having troubles interpreting the status register 7 of the altremote_update core in a Cyclone IV device.

My application:

* FPGA_BOOT -> offset 0x0

* FPGA_APP -> offset 0x20000

Typical flow is: power on -> FPGA_BOOT -> FPGA_APP

When starting FPGA_BOOT application, the status register 7 is checked.

If this application was loaded because of ...

• error condition when booting from FPGA_APP => stop reconfiguration, error message

• user triggered reconfiguration (FPGA_APP triggers boot from FPGA_BOOT) => perform tasks

• power on (first time, no errors, no user triggered reconfiguration) => boot from 2nd image

The error condition I am expecting to see is wrong CRC for FPGA_APP image (when image missing).

What I get:

* 2nd image missing -> I should get CRC errors -> status register shows 0! :cry:

* user triggered boot -> status register shows 0 again.

What am I doing wrong? Is this the way I am supposed to use this register?

I appreciate any help on this topic!

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Reading is done with a Nios2 and PIO components for each altremote_update component, as follows:

short int write_fpga_reconfig_param(int param_number, int param_value){
	IOWR_32DIRECT(PARAM_BASE, 0, param_number); 	// param address
	IOWR_32DIRECT(DATA_IN_BASE, 0, param_value); 	// param value (disable watchdog)
	IOWR_32DIRECT(WRITE_PARAM_BASE, 0, 0x1); 		// set write
	IOWR_32DIRECT(WRITE_PARAM_BASE, 0, 0x0); 		// clear write flag
	while(IORD_32DIRECT(BUSY_BASE, 0)); 			// wait for rising edge of busy
	return 1; 													// all writes are succesful...
}
int read_fpga_reconfig_param(int param_number){
	IOWR_32DIRECT(PARAM_BASE, 0, param_number); 	// param address
	IOWR_32DIRECT(READ_SOURCE_BASE, 0, 0x0); 		// source 0x2 (previous state reg 2 contents)
	IOWR_32DIRECT(READ_PARAM_BASE, 0, 0x1); 		// set read
	IOWR_32DIRECT(READ_PARAM_BASE, 0, 0x0); 		// clear read flag
	while(IORD_32DIRECT(BUSY_BASE, 0)); 			// wait for rising edge of busy
	return IORD_32DIRECT(DATA_OUT_BASE, 0/*
 * direct PIO control -> activate reconfiguration
 */
);
}
void trigger_fpga_reconfig(){
	usleep(100000);
	IOWR_32DIRECT(FPGA_RECONFIG_BASE, 0, 0x1); // trigger reconfig
}