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Altera_Forum
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13 years ago

ALTREMOTE_UPDATE error conditions

Hi, I am having troubles interpreting the status register 7 of the altremote_update core in a Cyclone IV device. My application: * FPGA_BOOT -> offset 0x0 * FPGA_APP -> offset 0x2000...
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Altera_Forum
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13 years ago

Hi Chris, thanks for the tip, now I am able to read the registers.

It looks well with the user-triggered reconfiguration (bit 0 is set),

but strange with the error-triggered configuration when 2nd image is missing. The code I am getting is 0x4 and this corresponds (quote from ds) 

nstatus_source: nSTATUS asserted by an external device as the result of an error

what I was expecting was 0x8 -> CRC error indication. which are the conditions for this bit to be set? does this have any connection with the "Enable error detection CRC" option from the "Device and Pin Options" menu?