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Altera_Forum
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14 years ago

altremote_update - cold-start issue

Hi, I'm having some problems with the altremote_update core on a Cyclone III FPGA. ===# 1 === - reconfiguration from application offset (0x080000) after cold-start of the system does not...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You are right. I browsed the CIII datasheet and I found that watchdog timer is actually driven by a 10MHz internal clock, while the user clock is only for register access.

However this means a 52sec timeout, which is far lower than your 3 minutes.