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Altera_Forum
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14 years ago

altremote_update - cold-start issue

Hi, I'm having some problems with the altremote_update core on a Cyclone III FPGA. ===# 1 === - reconfiguration from application offset (0x080000) after cold-start of the system does not...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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What's the clock frequency driving the remote update core?

For CIII it must be fclk<40MHz.

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the clock is 25 (and ok since I am able to change boot address and reconfigure).

one susicion: the clock is fed by a PLL and may not be available during and short after configuration. can this be an issue?