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The 2nd bit set (value=0x2) in register 7 for past status (read source 1), shows that fpga reconfigured because of a watchdog timeout.
If I remeber correctly the watchdog timer is automatically enabled in user configuration and disabled in factory configuration. So you need to explicitly disable or periodically reset it when the application image has been loaded (and preferably after you have checked it is correctly operating).
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Thanks! It was the watchdog!
That's what I did and it worked. Both issues were solved with this.
:(Altera needs to revise documentation for some cores... especially this one.
Honored Contributor
