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Altera_Forum
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12 years ago

altpll_reconfig on Arria II GX Produces Unexpected Results

I have implemented an altlvds_rx receiver with extranl PLL in an Arria II GX device. The PLL includes optional inputs for Dynamic Configuration. I added an altpll_reconfig block to change the altlvds_rx data rates on the fly, as well as a state machine to generate the required "reconfig" pulse. When simulating with ModelSim ASE, the PLL outputs are correct prior to being reconfigured. After reconfiguration, the PLL output frequencies and duty cycles are not as expected.

The altpll_reconfig block has an initial value specified for the scan chain (a .mif file produced by the altpll wizard), and has the "initialize from ROM" box checked.

To aid in debugging, I created a PLL config file (.mif) which matches the default PLL parameters, so there should be no change to the PLL outputs when reconfigured. Reconfig during simulation still produces bad outputs. This happens on Quarus II 12.1 and Quartus II 13.0sp1.

The issue appears to be specific to the Arria II GX implementation: if I change the device to a Cyclone III and re-instance altpll, altpll_reconfig and the .mif, simulation works properly.

Has anybody been successful using the altpll_reconfig IP on an Arria II GX? None of Altera's examples target this device.

Thanks!

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Note that during simulation, the Transcript window shows some register values (N, M, Charge Pump Current, etc.) do not change, while others (C0 through C6) do. None should change, since the .mif file represents the default contents of the PLL registers.

    # ** Note: PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :

    # Time: 6210938 ps Iteration: 0 Instance: /h_fpga/\inst|altpll_component|auto_generated|pll1

    # N modulus = 7 ( 7 )

    # M modulus = 86 ( 86 )

    # M ph_tap = 0 ( 0 )

    # clk1 : C0 : high = 256 (3) , low = 256 (3) , mode = even ( even) , phase tap = 0 (0)

    # clk0 : C1 : high = 1 (2) , low = 5 (1) , mode = even ( odd) , phase tap = 0 (0)

    # clk4 : C2 : high = 3 (3) , low = 3 (3) , mode = even ( even) , phase tap = 0 (0)

    # clk6 : C3 : high = 256 (3) , low = 256 (3) , mode = bypass ( even) , phase tap = 0 (0)

    # clk2 : C4 : high = 3 (16) , low = 3 (16) , mode = even (bypass) , phase tap = 0 (0)

    # clk3 : C5 : high = 3 (16) , low = 3 (16) , mode = even (bypass) , phase tap = 0 (0)

    # unused : C6 : high = 2 (1) , low = 1 (5) , mode = odd ( even) , phase tap = 0 (0)

    # Charge Pump Current (bit setting) = 1 ( 1 )

    # Loop Filter Capacitor (bit setting) = 0 ( 0 )

    # Loop Filter Resistor (bit setting) = 20 ( 20 )

    # VCO_Post_Scale = 1 ( 1 )

    # ** Note: PiranhaIII PLL locked to incoming clock