altpll_reconfig on Arria II GX Produces Unexpected Results

Note that during simulation, the Transcript window shows some register values (N, M, Charge Pump Current, etc.) do not change, while others (C0 through C6) do. None should change, since the .mif file represents the default contents of the PLL registers.

# ** Note: PLL Reprogramming completed with the following values (Values in parantheses indicate values before reprogramming) :

# Time: 6210938 ps Iteration: 0 Instance: /h_fpga/\inst|altpll_component|auto_generated|pll1

# N modulus = 7 ( 7 )

# M modulus = 86 ( 86 )

# M ph_tap = 0 ( 0 )

# clk1 : C0 : high = 256 (3) , low = 256 (3) , mode = even ( even) , phase tap = 0 (0)

# clk0 : C1 : high = 1 (2) , low = 5 (1) , mode = even ( odd) , phase tap = 0 (0)

# clk4 : C2 : high = 3 (3) , low = 3 (3) , mode = even ( even) , phase tap = 0 (0)

# clk6 : C3 : high = 256 (3) , low = 256 (3) , mode = bypass ( even) , phase tap = 0 (0)

# clk2 : C4 : high = 3 (16) , low = 3 (16) , mode = even (bypass) , phase tap = 0 (0)

# clk3 : C5 : high = 3 (16) , low = 3 (16) , mode = even (bypass) , phase tap = 0 (0)

# unused : C6 : high = 2 (1) , low = 1 (5) , mode = odd ( even) , phase tap = 0 (0)

# Charge Pump Current (bit setting) = 1 ( 1 )

# Loop Filter Capacitor (bit setting) = 0 ( 0 )

# Loop Filter Resistor (bit setting) = 20 ( 20 )

# VCO_Post_Scale = 1 ( 1 )

# ** Note: PiranhaIII PLL locked to incoming clock