Forum Discussion
Altera_Forum
Honored Contributor
8 years agoHi, gj_leeson!
I have the same problem: on one pin may be clock 25MHz or 125MHz and I have a pin, which indicates this - 0 for 25 and 1 for 125. I read altera manuals about altpll_reconfig with several mif-files. I create the same scheme with two ROMs, MUX, pll_reconfig and pll. I create two mif-files from pll wizard for two input clocks. And my question: how should I configure the pll? The default PLL settings are for 125MHz, because this situation is more difficult for scheme and TimeQuest timing analyzer. Am I right or not? What would you advise in this case? Thanks!