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Altera_Forum's avatar
Altera_Forum
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14 years ago

Altmemphy and DDR question

Where can I find timing info for Altmemphy. I am trying to do signal integrity analysis of FPGA and DDR2 interface. I need clock to DQS delay min/max, DQmin, max etc.

I am a bit confused about the clock frequency of DDR vs DDR2.

For example, for DDR-400, the data rate is 400Mbps and for DDR2-400 the data rate is 400Mbps

For DDR-400, the memory clock is 200MHz.

For DDR2-400, the memory clock is 200MHz?????????????

By Memory clock, I mean the clock frequency that comes from the external memory controller like an FPGA.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I'm a beginner myself but I believe you need the timing info from the memory chip datasheet and use these in the sdc constraints so that the fitter can optimize the paths to accommodate the latencies.

    The numbers in both DDR-400 and DDR2-400 stand for the maximum amount of transfers per second which is the same 400MT/s for both modules.

    For DDR this gives a transfer rate of (internal memory clock rate) × 2 (DDR) × 64 (number of bits per transfer) / 8 (bits per byte)

    For DDR2 this gives a transfer rate of 2 x (internal memory clock rate) × 2 (DDR) × 64 (number of bits per transfer) / 8 (bits per byte)

    But since the internal memory clock of DDR2 is two times lower, they both result in the same throughput. For both modules, the externally applied I/O clock rate is 200Mhz for both modules.

    In short, DDR-X and DDR2-X memories with the same value X have the same maximum data rate and the same externally applied clock rate of X/2. Difference is that the internal memory clock of DDR2 is two times lower than the one of DDR and most likely some differences in internal latencies.

    N.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    I'm a beginner myself but I believe you need the timing info from the memory chip datasheet and use these in the sdc constraints so that the fitter can optimize the paths to accommodate the latencies.

    --- Quote End ---

    I am looking for timing after the fitter optimizes the paths. The tool I am using for signal integrity simulation is hyperlynx. I need to enter the timing info of the controller to get any timing violation if any.

    --- Quote Start ---

    The numbers in both DDR-400 and DDR2-400 stand for the maximum amount of transfers per second which is the same 400MT/s for both modules.

    For DDR this gives a transfer rate of (internal memory clock rate) × 2 (DDR) × 64 (number of bits per transfer) / 8 (bits per byte)

    For DDR2 this gives a transfer rate of 2 x (internal memory clock rate) × 2 (DDR) × 64 (number of bits per transfer) / 8 (bits per byte)

    But since the internal memory clock of DDR2 is two times lower, they both result in the same throughput. For both modules, the externally applied I/O clock rate is 200Mhz for both modules.

    In short, DDR-X and DDR2-X memories with the same value X have the same maximum data rate and the same externally applied clock rate of X/2. Difference is that the internal memory clock of DDR2 is two times lower than the one of DDR and most likely some differences in internal latencies.

    N.

    --- Quote End ---

    Regarding the transfer rate, why do you multiply by 64?

    For DDR3-800, the external clock would be 800/2 = 400MHz?

    But wiki says, DDR3-800 Memory clock speed is 100MHz?:eek: