Forum Discussion
New ContributorALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.
Hi,
I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.
With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.
Thanks for everybody feedback!
Best Regards.
New ContributorIt seems the fitting works when different banks are used. I checked the Stratix IV (which the complete synthesis is success) and the pin assigment has pins in different banks for same TX bus using LVDS. Please, check the screenshot. It uses 5C and 5A banks. Why in this case there is no clock tree complaining?
Frequent ContributorTo be precise the Stratix V and And Stratix IV are having different architecture that is the reason
And to answer the above thread questions, I have a suggestion to try different LVDS IP for each bank and the clock source.
