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CFDia's avatar
CFDia
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7 years ago
Solved

ALTLVDS_TX is not able to handle clock tree and assignments during fitting synthesis.

Hello Folks, I have a Quartus custom (no-OS) project for a Stratix IV board which works with an AD9361 daugther board. The project synthesize perfectly and I able to use AD9631 as it should be. Now...
  • CFDia's avatar
    CFDia
    6 years ago

    Hi,

    I have finally found a way around. I just gave up using LVDS for Stratix V. Instead, I used CMOS and ended up rewriting the HDL. It is now working like a charm, but I still need to fix some minor issues.

    With respect to the LVDS, the problem were actually the pins in different banks. It is not possible to "link together" the same clock tree for different banks.

    Thanks for everybody feedback!

    Best Regards.

CFDia's avatar
CFDia
Icon for New Contributor rankNew Contributor
7 years ago

Hello RSree,

Thanks for your reply. What do you mean with compact to the Stratix V? Would you mind tell me what is it?

I checked assigment table from Stratix V development board. What else should I check beyond pin assigment and LVDS. I am quite sure that they are correctly assigned.

Is there anything on Megafunction properties that I should change?

Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
7 years ago

Hi,

The Pin assignment I mean,is that correct is it correctly assigned .By mistake it is not assigned to any transceiver pins.

If possible can you please send a sample project which makes the error so that I can comment what is the exact issue.

Re