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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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With DPA, each channel is dynamically captured, so no matter what your trace length is, you will get clean data. The problem is that the data from adjacent channels is not necessarily aligned, so the closer your trace lengths the less difference there will be when entering the fabric.

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Hi Rysc,

Thanks for you reply quickly.

1. For i want to combine 3 ADC chips output into one alt-lvds receiver module, i have chose one of these 3 ADC chips DCO to feed into fpga. Do you think which one selected is better, or anyone is ok?

2. In order to save LVDS RX pins, can i only connect one of three FCO into fpga? Even i have enough lvds-rx pins to reciever all three fco, i just want to know if i can combine more than 3 ADC chips into one alt-lvds reciever module.

Best Regard