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Altera_Forum
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9 years ago

ALTLVDS_RX->LVDS serdes Link Training

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for lin...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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If you can close static timing then bit alignment is not needed - it's already done. If you can do that at 576Mbps you're a better engineer than I am!

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It rather depends on the transmitting device. Unfortunately the OP didn't tell us what device it is. I have closed 600 Mbps in Cyclone II, the source devices were TI octal ADCs using a home-made deserialiser. Here is an image of the board with 16 ADCs:http://c-cam.be/images/img_7.jpg (http://c-cam.be/images/img_7.jpg)