ALTLVDS_RX input clock jitter mitigation

We are using ALTLVDS_RX on a Arria V type FPGA to receive data from a MIPI D-PHY device as described in https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an754.pdf

In this particular configuration, we are receiving MIPI at 300 MHz (600 Mbps) on 2 data lanes (and 1 clock lane). The differential MIPI clock is connected to ALTLVDS_RX input clock port. For ALTLVDS_RX we are using the following configuration when generating from the GUI.

• Number of channels is 4
• Deserialization factor is 8
• No external PLL
• Input clock rate 300 MHz
• "Use 'pll_areset' input port" enabled
• "Use 'rx_locked' output port" enabled
• "Regional clock" for 'rx_outclock' clock resource
• 90deg phase alignment of 'rx_in' with respect to 'rx_inclock'
• "Register outputs" enabled

With this setup we can normally successfully receive from MIPI D-PHY device.

However, we occassionally get bit errors in the data received which results in ECC/CRC errors on MIPI level. We have performed board level measurments and found a correlation between occurrance of ECC/CRC errors and increased jitter in the MIPI clock (ALTLVDS_RX input clock). Interestingly, the ALTLVDS_RX PLL maintains its lock status in this case, but there is probability that some bits are not transmitted properly.

We have the following questions

1. Is it feasible for input clock jitter on ALTLVDS_RX to lead to false capturing of the input data while the PLL maintains its lock? We are currently assuming that jitter on ALTLVDS_RX input clock has some effect on ALTLVDS_RX output clocks which leads to the capturing errors.
2. Are there any ALTLVDS_RX settings that we can make to mitigate the effect of jitter in the input clock? We were also thinking of using ALTLVDS_RX in "external PLL mode" so we have more control over specific PLL settings.

Thanks