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Altera_Forum's avatar
Altera_Forum
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16 years ago

ALTGX the cal_blk_clk signal, what is it?

Please help with a simple query.

I set up a ALTGX using the wizard tool, the pll_inclk signal is the reference clock that is multiplied by PLL to make tx_clkout[0] and time the serial data right? So what is cal_blk_clk ? if I use 100Mhz clock for pll_inclk what do I connect to cal_blk_clk ?

Thanks for any help

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hi,

    The cal_blk_clk is the clock for the calibration block of the ALTGX.

    In the stratix IV it should be between 10 MHz and 125 MHz.

    (It is described in the Handbook vol 2 of the corresponding device )

    "The calibration block internally generates a constant internal reference voltage,

    independent of process, voltage, or temperature variations. It uses the internal

    reference voltage and external reference resistor (you must connect the resistor to the

    RREF pin) to generate constant reference currents. These reference currents are used

    by the analog block calibration circuit to calibrate the transceiver blocks.

    "

    Cheers
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Hello,

    i want to know how much space it require for the WIN CE OS on a DDR?

    a)How much it requires for read/write in mobile DDR?

    Regards

    Vinoth.