Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

ALTGX PIPE lane deskew?

How is lane deskew done for a x4 link in ALTGX in PIPE (Pci Express) mode? The deskew FIFO is not used except for XAUI mode. My FPGA (Arria II GX) will snoop on a link where the training sets (TS1, TS2) have already been sent.

This is for a PCIe Protocol Analyzer design where the skew due to trace length differences is not known. I'm trying to find out whether I need to do anything to guarantee that lane-to-lane skew doesn't cause data corruption. Apparently, a bonded link must handle up to 20ns of lane-to-lane skew. How is this done in the ALTGX in PIPE mode?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I have found that I must implement my own lane deskew logic based on COM+SKP+SKP+SKP ordered sets that are received on all lanes in parallel. To do this, I must detect the number of symbols that need to be delayed based on the distance of the COM symbols on the different lanes. Interesting problem apparently since there are a number of patents describing possible solutions.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    --- Quote Start ---

    I have found that I must implement my own lane deskew logic based on COM+SKP+SKP+SKP ordered sets that are received on all lanes in parallel. To do this, I must detect the number of symbols that need to be delayed based on the distance of the COM symbols on the different lanes. Interesting problem apparently since there are a number of patents describing possible solutions.

    --- Quote End ---

    Can you give me some hint or documentation about how to solve the deskew? I was stuck at this problem for a while.