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Altera_Forum
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14 years ago

ALTGX PIPE lane deskew?

How is lane deskew done for a x4 link in ALTGX in PIPE (Pci Express) mode? The deskew FIFO is not used except for XAUI mode. My FPGA (Arria II GX) will snoop on a link where the training sets (TS1, T...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I have found that I must implement my own lane deskew logic based on COM+SKP+SKP+SKP ordered sets that are received on all lanes in parallel. To do this, I must detect the number of symbols that need to be delayed based on the distance of the COM symbols on the different lanes. Interesting problem apparently since there are a number of patents describing possible solutions.