Alterra embedded example::>Altera-SoCFPGA-HardwareLib-FPGA-CV-ARMCC::>FAIL ONRESET A9

Sorry for a late reply,

Yes, apparently you are using Arrow board. Altera has it's own development board: cyclone v soc development kit (http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html) and the examples are made for that board (note small differences in names between them, for HardwareLib example's readme.txt mentiones MSEL, on Arrow board it is called BOOTSEL).

There are 3 modes of booting the system:

• FPGA first

• HPS first

• Independent

as described in cyclone v device handbook: booting and configuration (http://www.altera.com/literature/hb/cyclone-v/cv_5400a.pdf). I believe that HardwareLib example boots HPS first and then loads FPGA image, but there is a line in readme.txt describing how MSEL pins must be configured.

Here is my code for Blinky I managed to run on FPGA project created from HW_Lab (Based on Hello World Baremetal with some files from preloader):

# include <stdio.h>
# include "alt_address_space.h"
# include "alt_bridge_manager.h"
# include "alt_clock_manager.h"
# include "alt_reset_manager.h"
# include "alt_dma.h"
# include "socal/socal.h"
# include "hwlib.h"
/*#include "hw_inits.h"*/
# include "pll_config.h"
# include "clock_manager.h"
# include "socfpga_base_addrs.h"
//#define ALT_FPGA_ENABLE_DMA_SUPPORT
/*
//	Protoype definition of main()
int main(int argc, char** argv);
//----------------------------------------
//		ENTRY POINT
//---------------------------------------
int __main(void){
	main(0,0);
	return 0;
}*/
# define ALT_LWFPGA_BASE         	0xFF200000
# define ALT_LWFPGA_SYSID_OFFSET 	0x00010000
# define ALT_LWFPGA_LED_OFFSET   	0x00010040
# define DW_WDT_CR	0x00
# define DW_WDT_TORR	0x04
# define DW_WDT_CRR	0x0C
# define DW_WDT_CR_EN_OFFSET	0x00
# define DW_WDT_CR_RMOD_OFFSET	0x01
# define DW_WDT_CR_RMOD_VAL	0x00
# define DW_WDT_CRR_RESTART_VAL	0x76
int i=0;
void delay(int loops){
	for(i=0; i<loops;i++){
		__asm__("nop");
	}
}
int main(int argc, char** argv) {
 //
    //ALT_DMA_CHANNEL_t channel;
	printf("Hello from Semi-Hosted ARMCC Baremetal Altera SoC-FPGA!\n");
	ALT_STATUS_CODE status = ALT_E_SUCCESS;
	if( status == ALT_E_SUCCESS) {
		status = alt_bridge_init(ALT_BRIDGE_F2H,0,0);
	} else {
		while(1);	// catch error
	}
	if( status == ALT_E_SUCCESS) {
		status = alt_bridge_init(ALT_BRIDGE_H2F,0,0);
	} else {
		while(1);	// catch error
	}
	if( status == ALT_E_SUCCESS) {
		status = alt_bridge_init(ALT_BRIDGE_LWH2F,0,0);
	} else {
		while(1);	// catch error
	}
	if( status == ALT_E_SUCCESS) {
	    status = alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM,
	                                  ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM,
	                                  ALT_ADDR_SPACE_H2F_ACCESSIBLE,
	                                  ALT_ADDR_SPACE_LWH2F_ACCESSIBLE);
	} else {
		while(1);	// catch error
	}
	while(1){
		alt_write_word(ALT_LWFPGA_BASE + ALT_LWFPGA_LED_OFFSET, 0x3);
		delay(10000);
		alt_write_word(ALT_LWFPGA_BASE + ALT_LWFPGA_LED_OFFSET, 0x0);
		delay(10000);
		// reset watchdog timer
		alt_write_word((SOCFPGA_L4WD0_ADDRESS + DW_WDT_CRR), DW_WDT_CRR_RESTART_VAL );
	}
	return 0;
}