Altera Soft LVDS IP core (output not consistent with the input)

Hi SMS,

I prefer to think about FCO and DCO as outputs of, for example, ADC.

For example, you can check here -

https://www.analog.com/media/en/technical-documentation/data-sheets/AD9287.pdf Figure 2.

In that case, FCO is typically edge aligned with data, but DCO is not.

So if you will look at that manual (Figure 15. Data Realignment Timing)

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_lvds.pdf

you can see that here rx_inclock is aligned wth rx_in, but is slower than data change rate.

So I think in your case you better use FCO than DCO. I also will advise to assure that you have correct timing relationship between inclock and rx_in. By the way, could you try simulation as it is in Case I but trying slightly to shift inclock (less than quater period as in Case II)?

Best regards,

Ivan