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SMS
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7 years ago

Altera Soft LVDS IP core (output not consistent with the input)

I am simulating the Soft LVDS IP core as receiver by passing a bit stream with IP core parameters configured as follows: Power Supply Mode: Dual (for 10M50DAF484C7G) Functional mode: RX Number of ...
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SMS
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7 years ago

I have been assuming up till now that rx_inclock is DCO and rx_outclock is FCO, please correct me if I am wrong. And since FCO is generated by the IP core itself I can only control DCO and the serial data input. Given this I have tried following three cases for data rate of 200 Mbps, rx_inclock of 200 MHz and with serial input 8'hAA:

Case I:

serial data input is aligned with positive edge of DCO:

Case II:

serial data input is aligned with quarter period of the DCO:

Case III:

serial data input is aligned with half period of the DCO: