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Honored Contributor
Honored ContributorAltera PLL timequest nets
Hello, I have an Integer PLL instantiated in my Cyclone V SOC design. In Timequest, I noticed 2 possible nets to choose from for this PLL: 1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Is there any way to make Timequest name this clock after the HDL net name connected to it ? --- Quote End --- Unfortunately, no. That's the caveat for using derive_pll_clocks. If you want to give the derived clocks custom names to make them easier to recognize in reports and use in other constraints, generate an SDC report (or write out an SDC file with the -expand option enabled) to see the standard create_generated_clock commands for your PLL outputs. Then add the -name option to those constraints with the names you want to use.
