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Honored Contributor
Honored ContributorAltera PLL timequest nets
Hello, I have an Integer PLL instantiated in my Cyclone V SOC design. In Timequest, I noticed 2 possible nets to choose from for this PLL: 1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I assume you are talking about creating a generated clock for the output of the PLL. Instead of doing that, just use derive_pll_clocks. That automatically creates all the clock constraints for all PLL outputs, assuming you've constrained the input reference clocks. --- Quote End --- No. I used "derive_pll_clocks" and: 1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[0]" Are the names the tool gave to the PLL output clock.
