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Altera_Forum
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9 years ago

Altera PLL timequest nets

Hello, I have an Integer PLL instantiated in my Cyclone V SOC design. In Timequest, I noticed 2 possible nets to choose from for this PLL: 1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[...
Altera_Forum's avatar
Altera_Forum
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9 years ago

I assume you are talking about creating a generated clock for the output of the PLL. Instead of doing that, just use derive_pll_clocks. That automatically creates all the clock constraints for all PLL outputs, assuming you've constrained the input reference clocks.