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Altera_Forum's avatar
Altera_Forum
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13 years ago

Altera PLL 12.0 or 12.1 with Cyclone V

Hi, my name is Jean and I use Cyclone V for my design.

I use a Altera PLL (version 12.1) to have a 100MHz clock from 10MHz base clock (Reference Clock).

My reference clock is a gclock and when I simulate this PLL (with ModelSim), no output work (No Lock and no output clock)!!

I have made a reset (low, high and low) and I have any result !!!!!

I have made the same thing with Cyclone IV and altpll and it work fine.

Do you have any Idea ?

It's Altera ModelSim or me :) ?

Thank you

The operation mode is Normal or direct, PLL Mode is Integer-N PLL.

One output Clock at 100MHz

Reference clock at 10MHz

The result is (from ModelSIm, outclk_0 = the output of PLL):

** Warning: (vsim-8684) No drivers exist on out port /tb_testalgo/b2v_inst/outclk_0, and its initial value is not used.

** Warning: (vsim-8684) No drivers exist on out port /tb_testalgo/b2v_inst/locked, and its initial value is not used.

Jean

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    also, When I compile my test design, I have a warning:

    Warning (332056): PLL cross checking found inconsistent PLL clock settings:

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[1] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[2] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[3] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[4] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[5] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[6] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000

    Warning (332056): Node: inst|testpll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[7] was found missing 1 generated clock that corresponds to a base clock with a period of: 100.000
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Other warning when I compile:

    10034 Output port "phout" at altera_pll.v (275) has no driver

    10034 Output port "cascade_out" at altera_pll.v (275) has no driver