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Altera_Forum
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9 years ago

Altera Modelsim vsim-3601

Hi everyone!

When i start simulation in quartus the following error message appear:

"(vsim-3601) Iteration limit 5000 reached at time 0 ps"

My testbench is: 


`timescale 1 ns/ 1 nsmodule buffer_vlg_tst();
reg CLK_50MHz;                                            
wire   data_out;
                          
buffer i1 (   
          .CLK_50MHz(CLK_50MHz),
          .data_out(data_out)
             );
initial                                                
begin
    CLK_50MHz=1'b1;                                                                                                                    
    $display("Running testbench"); 
     forever# 20 CLK_50MHz= ~CLK_50MHz;
end

Any thoughts would be very helpful. Thanks!

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    --- Quote Start ---

    whats the code inside the buffer module?

    --- Quote End ---

    The code is: 

    
macromodule buffer (
					input CLK_50MHz,
					output  data_out
					);
					
wire  data_count;
					
counter count (
					.clock(CLK_2KHz),
					.q(data_count));
					
pll my_pll 		(
					.inclk0(CLK_50MHz),
					.c0(CLK_2KHz),
					.c1(CLK_8KHz));
					
serializer serial (
					.clk(CLK_8KHz), /*start,*/ 
					.inp_data(data_count), 
					.out_data(data_out), 
					.capture(CLK_2KHz));
					
endmodule
module serializer(clk, inp_data, out_data, capture);
input clk, capture;
input   inp_data;
output  out_data;
reg  counter;
reg  out_data;
reg  temp_data;
always @(posedge capture) temp_data <= inp_data;//input data bufferization
always @(posedge clk)
begin
	counter <= 2;
	counter <= counter + 1'b1;
end
always @(posedge clk)
begin
	case(counter)
		2'd0: out_data <= temp_data;	//2
		2'd1: out_data <= temp_data;	//1
		2'd2: out_data <= temp_data;	        //4
		2'd3: out_data <= temp_data;	//3
	endcase
end
endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    Tricky, the code is: 

    
macromodule buffer (
					input CLK_50MHz,
					output  data_out
					);
					
wire  data_count;
					
counter count (
					.clock(CLK_2KHz),
					.q(data_count));
					
pll my_pll 		(
					.inclk0(CLK_50MHz),
					.c0(CLK_2KHz),
					.c1(CLK_8KHz));
					
serializer serial (
					.clk(CLK_8KHz), /*start,*/ 
					.inp_data(data_count), 
					.out_data(data_out), 
					.capture(CLK_2KHz));
					
endmodule
module serializer(clk, inp_data, out_data, capture);
input clk, capture;
input   inp_data;
output  out_data;
reg  counter;
reg  out_data;
reg  temp_data;
always @(posedge capture) temp_data <= inp_data;//input data bufferization
always @(posedge clk)
begin
	counter <= 2;
	counter <= counter + 1'b1;
end
always @(posedge clk)
begin
	case(counter)
		2'd0: out_data <= temp_data;	//2
		2'd1: out_data <= temp_data;	//1
		2'd2: out_data <= temp_data;	        //4
		2'd3: out_data <= temp_data;	//3
	endcase
end
endmodule
  • Altera_Forum's avatar
    Altera_Forum
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    9 years ago

    You have a forever statement inside the initial block. The initial block is for things that happen at time 0. You can't have something go on forever at time 0.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    --- Quote Start ---

    You have a forever statement inside the initial block. The initial block is for things that happen at time 0. You can't have something go on forever at time 0.

    --- Quote End ---

    In a testbench, initial blocks can be used to drive stimulus during simulation for example - a reset: 

    
initial begin
        rst = 1;
        repeat(5) @ (posedge clk) ;
        rst = 0;
    end

    But the OP has generated the clock incorrectly. By using# 5 on the assignment, you only delay the assignment, not the loop, causing the 5000 iteration limit as it is trying to assign the clock at time zero. To do it correctly in an inital block: 

    
inital begin
  forever begin 
    CLK_50MHz= ~CLK_50MHz;
   # 20;
  end
end