Altera Modelsim vsim-3601

macromodule buffer (
					input CLK_50MHz,
					output  data_out
					);
					
wire  data_count;
					
counter count (
					.clock(CLK_2KHz),
					.q(data_count));
					
pll my_pll 		(
					.inclk0(CLK_50MHz),
					.c0(CLK_2KHz),
					.c1(CLK_8KHz));
					
serializer serial (
					.clk(CLK_8KHz), /*start,*/ 
					.inp_data(data_count), 
					.out_data(data_out), 
					.capture(CLK_2KHz));
					
endmodule
module serializer(clk, inp_data, out_data, capture);
input clk, capture;
input   inp_data;
output  out_data;
reg  counter;
reg  out_data;
reg  temp_data;
always @(posedge capture) temp_data <= inp_data;//input data bufferization
always @(posedge clk)
begin
	counter <= 2;
	counter <= counter + 1'b1;
end
always @(posedge clk)
begin
	case(counter)
		2'd0: out_data <= temp_data;	//2
		2'd1: out_data <= temp_data;	//1
		2'd2: out_data <= temp_data;	        //4
		2'd3: out_data <= temp_data;	//3
	endcase
end
endmodule