Altera_mm_interconnect functionality

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Transfer sizes are based on the data width, not the addressing. So if your data is 256 bits on both the master and slave sides, it will take two cycles to perform two writes, barring any latency options or pipeline settings.

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Thanks for your reply.

I mentioned wrong data width in output side.Actually input data width is 256 bit output data width is 512. So will it club two 256 data and send one packet of 512 bit for 2 beat burst transfer.

In my simulation it is not clubbing. For every beat it is generating 512 bit data.

Data - 'h55 ,'h66 (which i am sending)

Beat

Address (Input of interconnect)

Address (output of interconnect)

Data(Input of Interconnect)

Data(output of Interconnect 512 bit)

|MSB(256 bit) | LSB (256 bit)|

0

64'b0000_0010_0000_0000(Base address )

30'h0

256'h55

'h | all zeros | 000000055|

1

30'h0

256'h66

'h | 000066 | all zeros |

So the final value of address zero in slave side is 512'h 000066_00000000000000000000.. The data 55 is lost . Interconnect is generating this type of write.It is not clubbing the two 256 bit data.

Is it bug in interconnect or any other mask signal is needed for this transaction(like byteenable).

Thanks & Regards

Muthuvenkatesh