Altera_mf.v error

Hi all,

i added in my design a PLL. i ran a simulation, and all worked fine.

when i tried to do synthesis, i got an error - "Error (10853): Verilog HDL error at altera_mf.v(43479): argument 0 to $readmemh must be a string literal"

here is the code refferd to:

`ifdef NO_PLI

$readmemh(lpm_file, mem_data);

`else

`ifdef USE_RIF

$readmemh(lpm_file, mem_data);

`else

mem.convert_to_ver_file(lpm_file, width, ram_initf);

$readmemh(ram_initf, mem_data);

`endif

`endif

many thanks,

David