Altera MAX10 I/O pin performance confusion

Hello,

I am designing Altera max10 motor control board that will use 1MHz PWM as well as >100MHz LVDS comunication with controller. I need lot of CMOS (2.5-3.3V) pins capable more than 1-10MHz ( just for safety and peace of mind)

i was unable to find any data on this High speed and low speed GPIO, how they are different ? ( Ok, high speed banks usually have true lvds drivers ( bottom bank) ) But how about single ended performance, how they are different, what is the jitter performance, and maximum safe frequency ?

On cyclone i should not use VREF pins as high speed io, i get that, but for normal low speed IO with no dedicated function for VREF and programming ?

So questiuon is, what is the difference ?

Quote from pins description guide Low speed:

"These are I/O pins. Low_Speed I/O pins have lower performance compared to High_Speed I/O pins.

Low_Speed I/O pins reside in Banks 1A.."

High Speed:

"These are I/O pins. High_Speed I/O pins have higher performance compared to Low_Speed I/O pins.

High_Speed I/O pins reside in Banks 2, 3, 4, 5, 6, and 7."