Altera_ForumHonored Contributor9 years agoAltera MAX10 I/O pin performance confusion Hello, I am designing Altera max10 motor control board that will use 1MHz PWM as well as >100MHz LVDS comunication with controller. I need lot of CMOS (2.5-3.3V) pins capable more than 1-10MHz ( j...Show More
Altera_ForumHonored Contributor9 years ago10 MHz is a low frequency for an FPGA. Every pin should be capable of that frequency.
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information