Hi, I am totally new to this FPGA world so please ignore my question if they seem basic or stupid. I want to interface 8 channel, 12 bits resolution ADC with at least 50 MSPS A/D FPGA. I went through Texas Instrument webpage which says: the hsmc-adc-bridge passive interconnect board enables the output of ti’s lvds output high speed adcs to be directly connected to a standard hsmc interconnect header, a typical input on the latest altera fpga evms. Can you tell me if Altera DE2-115 Development Board can be interfaced with ADS5281EVM via HSMC-ADC-Bride provided by Texas Instrument ? Altera DE2 Board: http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=165&no=502&partno=3 ADS5282EVM: http://www.ti.com/tool/ads5281evm HSMC-ADC-Bridge: http://www.ti.com/tool/hsmc-adc-bridge I appreciate your help. Thanks.

That certainly appears to be the case, yes. I've not used the ADC eval kit or bridge board you refer to but do have a DE2-115 board. I've had a look through the schematics for the DE2-115 and the bridge board and am happy they are intended to work together. Assuming it also correctly connects to their own evaluation boards as well, as they claim (I don't doubt it does!), I think you're winning.

Hi, Thanks for your reply. I am glad to know that they can work together. I am developing a test measurement unit with 8 channel A/D card, FPGA and DSP unit. The idea is to transfer the 8 channel data continuously from FPGA to DSP for further processing. This FPGA has enough computation power to do the job, right ? Where should I look for FPGA code to transfer the data to FPGA ? Thanks.

I'm sure, very sure, there will be enough grunt in the DE2-115's FPGA. As for the code - isn't that for you to write? Refer to the datasheet for the ADC. There are some very clear diagrams showing the relevant data stream signal timings. Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed, in the same way the datasheet refers to a 12x clock from which the data streams are generated. You may be restricted by the signals that are carried across the interconnect board. However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there. Regards, Alex

--- Quote Start --- Given it operates at a Double Data Rate (DDR) you will have to operate some of your logic at twice the clock speed, --- Quote End --- This statement is confusing: DDR means you have to capture (or emit) data at both the negative and positive edge of the clock. But this only happens at the 'periphery' of the FPGA. This 'job' is handled by the ALTDDIO_xxx primitives/functions provided by Altera. Inside the FPGA data is consumed (produced) at double the width of the physical bus but at the base clock speed. --- Quote Start --- However, assuming you do have access to LCLK, and it can be fed into a PLL on the FPGA, then everything you need to solve it is there. --- Quote End --- This particular ADC, the ADS5281 (I believe most of TI ADCs), has it LCLK shifted by 90 degrees so you can do without a PLL.

Hi, There is always some sample code provided by the vendor which could be modified to suit your application. I was asking for that code.

Altera FPGA with TI A/D EVM | Altera Community

15 Replies

Altera_Forum
Honored Contributor
12 years ago
I re-compiled my existing application for a EP4CE115F896C7 targeting TI ADS5281 12 bit octal ADCs sampling at 50 MHz, and met timing with reasonable slack of about 200 ps setup and hold.
Altera_Forum
Honored Contributor
12 years ago
Thanks Josyb.

I was afraid if I will end up buying the product not meeting design criteria. Now I am going to order DE2-115 Board and ADS5282 and look forward for the development.

It will be my first design project. Can you give me some advise to get a head start ?

Thanks.
Altera_Forum
Honored Contributor
12 years ago
Hi,

Referring to the DE2_115_User_manual_2013, page# 41;

additionally, when lvds is used as the i/o standard of the hsmc connector, the lvds receivers need to assemble a 100 ohm resistor between two input signals for each pairs.

I wonder if I have to assemble 100 Ohm resistor myself ? If yes how ? Wouldn't it be difficult to add extra resistor to HSMC ? At least, I didn't find any information if board has 100 Ohm resistor already.

Thanks.
Altera_Forum
Honored Contributor
12 years ago
The schematic shows the 100 ohm resistors as DNI (Do Not Insert) so there will be pads on the PCB to mount these resistors by yourself. I wasn't able to find an assembly drawing of the layout, but I guess they will will be located very near or even under the FPGA.
Altera_Forum
Honored Contributor
12 years ago
--- Quote Start ---
The schematic shows the 100 ohm resistors as DNI (Do Not Insert) so there will be pads on the PCB to mount these resistors by yourself. I wasn't able to find an assembly drawing of the layout, but I guess they will will be located very near or even under the FPGA.
--- Quote End ---

Thanks Josyb.

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Altera FPGA with TI A/D EVM

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