Altera emac: Is it TSE or designware?

HI Ranran, Yes, I suggest you go through the Arria V reference doc (av_54012.pdf) to get a better understanding of the overall architecture. HPS (hard processor system) = A combination of various harden functional IP blocks that include one ARM processor + many more smaller IP including the designware EMAC HPS is hardwired connected to EMAC IP and then to certain dedicated FPGA HPS IO pins. HPS also has other data connection path that can connect to FPGA core logic via HPS-FPGA bridge. In the FPGA core logic, user can then instantiate different IP block design like TSE IP or NIOS II In short, FPGA provides multiple ways for user to implement TSE solution 1) Use ARM processor in HPS -> EMAC in HPS -> FPGA HPS dedicated IO pins 2) Use ARM processor in HPS -> HPS-FPGA bridge -> TSE IP 3) Ignore ARM processor and HPS, use NIOS II processor -> TSE IP in FPGA core logic directly So, it's really up to you to choose the solution that best suits your application. Thanks. Regards, dlim