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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Altera emac: Is it TSE or designware?

Hello, I am a bit confused with altera emac. I need to use emac from HPS in arria V or cyclone V. Checking both TRM documentation of these FPGA, it is described (in each TRM , and also in memory m...
rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Hello Dlim,

I hope I can ask one more on this. I haven't yet checked the reference example, I feel like I still miss some background understanding on the subject.

What do you mean by "Looks like HPS ARM processor is able to connect to FPGA core then to TSE IP. " ?

What is the difference between HPS access to FPGA and HPS ARM access TSE IP ?

Is it that the first case means that TSE is already memory mapped to arm, while the second requires a bridge to HPS ?

Another thing, in arria v reference documentation (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-v/av_54012.pdf) I don't see any mention on TSE is the memory address map, so where can I find how to access TSE from ARM in documentation ?

Thanks!

ranran