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I guess i'd simply feed this 3-5mhz signal into a divide-by-n counter, to give me a clock in the order of 100'sHz to a few KHz.
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Even if you have lots of positive clock setup slack at these low frequencies, you have to be careful about clock hold at any frequency, especially if you will have any paths crossing to or from the divided-down clock domain. If you have all your logic on the divided-down clock and make it global, you'll probably be OK without having to do anything extra. See my posts at
http://www.alteraforum.com/forum/showthread.php?t=754 for more information.
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