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Altera_Forum
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9 years ago

ALTDDIO_OUT primitive usage internally

Hi, I am using the Output DDR interface in one of my submodules in the hierarchy. I see that the output register is not set in spite of me selecting the option "Registers powerup high". Also, ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks.

Yes, I used a custom RTL block and everything works well now.

Just curious - It does not throw out an error (or even a warning) when I use ODDR2 in the submodules. I have used ODDR2 (in submodules) using different (non-altera) FPGA design tools before, and it works fine there. A warning or error regarding this would have been better.

Thanks, anyway!