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Honored Contributor

10 years ago

ALTDDIO - 16bitx250MHz to 32bitx125MHz - Proper Timequest timing closure?

Hi, I'm using ALTDDIO to convert source-synchronous 16-bit/250 MHz data to 32-bit/125 MHz data. The device is a Cyclone V E. I'm trying to figure out how to properly constrain this interface. I have ...

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Altera_Forum

Honored Contributor

10 years ago

Hi, it might be worth having a look at AN433

https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an433.pdf

I think for source sync ddr you will also need some false paths and possibly some multicycles in your sdc to make sure the timing is analysing the correct edges.

Forum Discussion

ALTDDIO - 16bitx250MHz to 32bitx125MHz - Proper Timequest timing closure?

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