ALT_PLL and clock-crossing

Hi.

Some month ago I started to work with Altera system and FPGA's in general. However there are still many things I have problems with.

Currently I finished my system and it works the way I want. Now I want to make it work faster, but I have problems adding a PLL into my system.

I have a custom peripheral. It reads and writes from/to on-chip memory to generate some numbers and writes this numbers to SDRAM. I would like to maximize the speed of this peripheral, about 400 MHz would be actually perfect. At this point I see two major problems: the f[SUB]max [/SUB]of SDRAM on my board is 143 MHz and, according to benchmark, NIOS II/e will run properly at 170MHz (Cyclone IV). The NIOS cpu just writes some values to my peripheral slave registers (base addresses and start value), so I don't think it cause problems. But the SDRAM... Is that even possible to run my component, which is a Master for SDRAM, with higher speed? If so, do I have to use a MM-Clock-Crossing Bridge? Or maybe I have to implement a MM-Master with same clock as the SDRAM-slave?

I think this is it for now.... I guess I still have to learn much, realy don't know what to do at this point. Help would be appreciated.

Thank you. Vlad.

Edit:

Now I added a PLL by using megaplugin wizzard. The whole system clock is now 100 MHz. As a test I run "Hello World" template with NIOS II Eclipse IDE. However, it only works if I link all data to the SDRAM, on on-chip memory I get this:

Using cable "USB-Blaster [USB-0]", device 1, instance 0x00

Processor is already paused

Reading System ID at address 0x00421058: verified

Initializing CPU cache (if present)

OK

Downloading 07FE0000 ( 0%)

Downloading 07FE6F70 (76%)

Downloaded 28KB in 0.5s (56.0KB/s)

Verifying 07FE0000 ( 0%)

Verify failed between address 0x7FE0000 and 0x7FE5527

Leaving target processor paused

My on-chip memory should be large enough, 100 KB - 32 Byte reset (0x07FE0020 - 0x07FF8FFF). Does anybody where the problem is?

Thanks.