Agilex5 SDM_IO pull-up resistors

Hi Asaf,  

1. When is the internal 20 kΩ pull-up active?

The phrase "when the device is powered up" in the Pin Connection Guidelines refers to the state after VCCIO_SDM has fully ramped up, not during the ramp itself. More precisely:

Internal Agilex 5 circuitry pulls SDM_IO0, SDM_IO8, and SDM_IO16 weakly low through a 20 kΩ resistor. All other SDM_IO pins (i.e., SDM_IO1–7, SDM_IO9–15) are pulled weakly high during power-on.

The SDM pins with MSEL function are powered by the VCCIO_SDM power supply, and they have internal weak pull-up resistors.

So for SDM_IO13 specifically: once VCCIO_SDM is up, the internal 20 kΩ pull-up is active. During the ramp itself, the pin state is indeterminate until VCCIO_SDM reaches its operating level.

2. Is the "Direct to Factory Image" pin behavior you're seeing normal?

Yes, what you're observing is consistent with the documented behavior. Here's why:

The "Direct to Factory Image" function has a weak pull-down with 20 kΩ resistor as its configured pull-up/pull-down when assigned as an optional configuration pin.

However, SDM_IO13 (which you're using) has an internal 20 kΩ pull-up during power-on (before the SDM configures the pin for its assigned function). Once the SDM initializes and configures SDM_IO13 for the "Direct to Factory Image" function, the pin transitions to its configured state — which is a weak pull-down. This explains the pull-high during ramp-up followed by a pull-down after ~50 ms (which aligns with the SDM boot and configuration initialization window).

For reference: the FPGA POR delay + bootup sequence until nSTATUS high (AS Fast Mode) is 1.5–7.6 ms, and periphery image loading time from nSTATUS to CONF_DONE is 70–90 ms — so a transition at ~50 ms into the boot sequence is well within the normal configuration window.

3. Your SDM_IO13 with internal 20 kΩ pull-up and external 100 kΩ pull-down

During power-on (before SDM configures the pin), the internal 20 kΩ pull-up will dominate over your external 100 kΩ pull-down, so the pin will sit high — which is exactly what you're observing. The voltage divider ratio gives approximately: V = VCCIO_SDM × 100k / (20k + 100k) ≈ 0.83 × VCCIO_SDM pulled up, so the pin will be well above the logic-high threshold during ramp-up.

Once the SDM configures SDM_IO13 for "Direct to Factory Image," the internal pull switches to a 20 kΩ pull-down, and now both your external 100 kΩ and the internal 20 kΩ pull the pin low — so the pin goes low and stays low, which is the correct default behavior for this function.

By default, the external logic should provide logic low to this pin so that the application image becomes the default image of the device, and only switch to factory image if required.

So the behavior you're seeing — pin high during ramp-up, then transitioning low after ~50 ms — is completely normal and expected. Your 100 kΩ external pull-down is fine for ensuring the pin is firmly low once the SDM takes over, though note that for SDM_IO pins 0, 8, and 16 (which have internal pull-downs), the recommendation is to connect a 4.7 kΩ external pull-up to VCCIO_SDM — that specific recommendation doesn't apply to SDM_IO13, which has an internal pull-up during power-on.

Bottom line: your design is behaving correctly. No action needed.

Sources: Device Configuration User Guide Agilex™ 5 FPGAs and SoCs, Device Design Guidelines: Agilex™ 5 FPGAs and SoCs, I/O Standards and Features for Configuration Pins, Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs, Pin Connection Guidelines, Device Design Guidelines: Agilex™ 5 FPGAs and SoCs