New ContributorHi,
Your understanding is correct, is there anything else you not understand and I can clarified more ?
Regards,
Wincent_Intel
Regular ContributorHi,
1. Does the enable PCIe receive queues (P,NP,C) in bypass modes and handle flow control?
The credit interface is used to implement flow control for the data movement between the user application interface and each IP block. Each header type (P,NP,CPL) and data type (P,NP,CPL) has an independent credit interface. One data credit consists of 16 bytes. One header credit includes the TLP Header, 1DW prefix (if present) and the digest (if present).The 4.4.1.2.2. Credit Initialization
describes the credit initialization and update flow.
https://www.intel.com/content/www/us/en/docs/programmable/683501/21-4-4-0-0/tlp-bypass-mode.html
2. If so, is PCIe ordering rules for relaxed ordering implemented at the output of the receive queues before the TLP is passed on to the application layer?
the relaxed ordering Implemented on the RX side. This feature is always active. On the TX side, reordering is done by the application.
Let me know if this answering your question.
Regards,
Wincent_Intel
New ContributorHi,
Thanks for the quick reply.
I am referring to F-Tile Avalon® Streaming Intel®
FPGA IP for PCI Express* User Guide Updated for Intel® Quartus® Prime Design Suite: 22.4
IP Version: 8.0.0.
Section 3.3.2.1 says that RX flow control interface is optional and disabled by default in the IP GUI. Does the IP expect the application to maintain separate queues for data and headers for P,NP and C TLPs?
Is there a single flow control interface? If Relaxed ordering is implemented, NP and C TLPs cannot pass posted TLPs. So, why is the IP expecting separate flow control credits for the TLP types?
Thanks
