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Shubhall's avatar
Shubhall
Icon for New Contributor rankNew Contributor
3 years ago

Agilex not programming (E tile)

Hi, I am currently working Agilex FPGA (AGFB014R24B2E2V). For my design standalone GHRD I am able to program, but when I am adding the JESD example design to it, the following error is coming - E...
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi Shubhangi,

Good day.

After further checking it seems like it might be some issue with the VID settings.

Based on your Agilex part number, I believe you are using the Agilex F-Series FPGA devkit Production-2V.

For the VID setting, you are required to input below script/code to avoid Quartus from generating an error due to incomplete SmartVID settings.

Intel® Agilex™ F-Series FPGA Devkit User GuideIntel® Agilex™ F-Series FPGA Devkit User Guide

You may change the scripts listed below in you project QSF file.

Please ensure that there are no other similar settings with different values.

6.1. Add SmartVID settings in the QSF file6.1. Add SmartVID settings in the QSF file

For more information you may refer to below link:

Intel® Agilex™ F-Series FPGA Development Kit User Guide - 6.1. Add SmartVID settings in the QSF file

Please try this step and let me know if error still happen.

Thank you.

Best Regards,

ZulsyafiqH_Intel


  • Shubhall's avatar
    Shubhall
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi,

    I am really sorry for replying late.
    This error is not same as Case - Not able to program Agilex FPGA. Both are actually different errors, so the solution mentioned above does not work.
    This error I am getting when I chose to assign FMC_GBTCLK_M2C_p0 (AJ14) or FMC_GBTCLK_M2C_p1 (AR16) for the JESD transceiver clock (refclk_xcvr). However, when using FMC_REFCLK0_p (AT13) or FMC_REFCLK1_p (AK13) for JESD transceivers, it gives no programming error. and the board configures successfully.
    Kindly help me to understand why I can not use the FMC_GBTCLK_M2C_P pin for refclk_xcvr (transceiver clock).
    Please note - This error you can replicate by generating any JESD204B preset example design for Agilex and assigning FMC_GBTCLK_M2C_p0 (AJ14) or FMC_GBTCLK_M2C_p1 (AR16) for refclk_xcvr pin in the qsf file.
    Please let me know if more information required from my side.
    Thank you
    Regards
    Shubhangi