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nskim's avatar
nskim
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2 months ago

Agilex 7 R-Tile RBES FPGA – CXL Device Enumeration Failure with CXL IP Design Example

1. What is the failure symptom? Please elaborate on the failure symptoms in detail. The CXL device fails to enumerate when using the CXL Type-3 IP design example. •    lspci -vvv | grep 0ddb does n...
Programmable Logic Device
quality|reliability
JohnT_Altera's avatar
JohnT_Altera
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2 months ago

Hi,

 

May I know which board OPN are you using? Can you also share the board serial number?

 

1. Have you check what is the status of the CXL Phy Link on the FPGA? 

2. Has your server been tested to be working with CXL card before? 

3. Can you share with me your server information such server model, CPU use and RAM?

 

Thanks

  • nskim's avatar
    nskim
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    2 months ago

    Hi John,

    The board OPN is DK-DEV-AGI027RBES (Power Solution 2), and the serial number is AGIPCIe8020349.

    Regarding your questions:

    1. CXL PHY link status on the FPGA

    Yes, we have checked the CXL PHY link status on the FPGA, and it was functional.

    2. Previous validation of the server with a CXL card

    Yes, this server has been tested with the same CXL card before and was working correctly.

    3. Server information (model, CPU, and RAM)

    We tested on both SPR and EMR platforms. For the EMR platform, we are using a Supermicro SYS-221H-TNR with two Intel® Xeon® Gold 6538Y+ CPUs and four Samsung M321R8GA0BB0-CQKRH DDR5 DIMMs.

    • JohnT_Altera's avatar
      JohnT_Altera
      Icon for Regular Contributor rankRegular Contributor
      1 month ago

      Hi,

       

      2. Previous validation of the server with a CXL card

      Yes, this server has been tested with the same CXL card before and was working correctly.

      [JohnT] May I know which design was use to test it was working correctly? What is the changes performed?

       

      Thanks

      • nskim's avatar
        nskim
        Icon for New Contributor rankNew Contributor
        1 month ago

        Hi John,

        We tested the CXL Type-2/Type-3 IP design examples using Quartus 24.3. These design examples worked previously but now fail on this particular device.

        We noticed the issue around mid-October 2025, but no clear root cause has been identified so far. There is no visible physical damage to the FPGA, and the bitstream programs successfully; however, the CXL device does not enumerate in the system.