New Contributor
New ContributorHi Kian,
Thanks for your insights. Is there any width adaptor IP readily available with altera to support 128-bit Merging into 256-bit for write channel and 256-bit Splitting into 128-bit for read channel.
Regards
Suresh
Frequent ContributorHi Suresh,
Sorry for the delay, was out of office. Previously I took a look on this , unfortunately there is no ready IP that can directly address this issue , documentation only mentioned about user needs to add a width adaptation interconnect logic but I didnt see any like examples from this.
Initially thought maybe FIFO IP but on its own it does not have Write strobes (WSTRB) in AXI protocol for partial write so cannot be used directly. In other hand, i think you are already using the ACE5-Lite cache coherency translator or width adapter performing implicit RWR operations, converting partial 128-bit writes into full 256-bit cache line operations
Have you considered instead of F2H, using F2SDRAM bridge instead to write the USB directly to the SDRAM bypassing the cache coherency unit and its width requirements?
Otherwise, I think it is possible to use FIFO IP to handle the data packing and then using the ACE5 lite cache coherency translator IP to handle the transaction. You might need a custom state machine to manage the FIFO IP to wait for it to pack all the data 512bit? to avoid the RWR and trigger the translator when data 2x256bit is fulfilled.
Thanks
Regards
Kian
