New Contributor
Frequent ContributorHi Suresh,
Apologies for the delay in getting back. As for your questions so far this is what I found from the documentations
While the document states it supports partial writes , seems in the screenshot it has no guarantee it will respond on narrow data aligned with non 256bit. Main suspect might be the HPS Cache Coherency Unit/CCU is converting the partial writes into full width via read,modify,write (RMW) operation
So basically Agilex 5 HPS and CCU operate on 512-bit cache lines. From my understanding your USB logic is providing 128bit partial data via WSTRB to 256 Ace lite interface that uses 256 bits and in turn to the system that operates at 512bit cache line.
As ACE Lite interface is in coherent mode, CCU cannot pass a 128bit partial write directly to SDRAM since it is on 512 bit width. Thus this is where the RMW comes in where it reads 512 bit from cache or SDRAM(previous or some random data), then modify it and then applies your 128bits data(together with another 128bits garbage/random data) into that 512bit data and then write the entire 512bit to the MPFE and SDRAM controller.
If using full data 256bit in your custom data with 2 burst (AWLEN=1) to fulfill the full 512bit, does the issue happen, if full 512bit most probably CCU will not do any RMW here? If single burst probably the other half will still be some random 256bit data that CCU packed into 512 bit
Thanks
Regards
Kian
New ContributorHi Kian,
Thanks for your insights. Is there any width adaptor IP readily available with altera to support 128-bit Merging into 256-bit for write channel and 256-bit Splitting into 128-bit for read channel.
Regards
Suresh
Frequent ContributorHi Suresh,
Sorry for the delay, was out of office. Previously I took a look on this , unfortunately there is no ready IP that can directly address this issue , documentation only mentioned about user needs to add a width adaptation interconnect logic but I didnt see any like examples from this.
Initially thought maybe FIFO IP but on its own it does not have Write strobes (WSTRB) in AXI protocol for partial write so cannot be used directly. In other hand, i think you are already using the ACE5-Lite cache coherency translator or width adapter performing implicit RWR operations, converting partial 128-bit writes into full 256-bit cache line operations
Have you considered instead of F2H, using F2SDRAM bridge instead to write the USB directly to the SDRAM bypassing the cache coherency unit and its width requirements?
Otherwise, I think it is possible to use FIFO IP to handle the data packing and then using the ACE5 lite cache coherency translator IP to handle the transaction. You might need a custom state machine to manage the FIFO IP to wait for it to pack all the data 512bit? to avoid the RWR and trigger the translator when data 2x256bit is fulfilled.
Thanks
Regards
Kian
