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Nicole04's avatar
Nicole04
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Agilex 5 E-Series Ethernet with 1588 via HPS EMAC

Good day,

I would like to use the Hard Processor System (HPS) Ethernet Media Access Controller (EMAC) peripheral (with IEEE 1588) for a Gigabit Ethernet (GbE) port. I found the information for this in the Hard Processor System Technical Reference Manual - Agilex 5 SoCs (814346).

I will use an external PHY and SGMII Interface. I would thus route the signals through the FPGA IOs. Should I use the HSIOs or a Transceiver for the SGMII signals?

How should the MDIO signals be routed? the PHYs I use allow for up to 16 PHYs to be connected via one MDIO bus. Is it possible to combine a non-HPS and HPS GbE port over the same MDIO bus? The PHYs will have different addresses. How should I then route this bus?

Do I still need to use the Triple-Speed Ethernet IP when I use the EMAC?

Other Ips

8 Replies

  • Nicole04's avatar
    Nicole04
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi,

    How will the shared MDIO be set up in the platform manager for the TSE IP?

    Is it better to use an MDIO EMAC for the HPS EMAC connected ethernet link?

  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


  • Jeet14's avatar
    Jeet14
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    Hi


    Let me know if you have any query on this.


    Regards

    Tiwari


    • Nicole04's avatar
      Nicole04
      Icon for Occasional Contributor rankOccasional Contributor
      4 months ago

      Good day,

      I have an SGMII connection to an XCVR which I would like to connect to the HPS EMAC. I am unsure how to set up the soft logic for the SGMII to GMII bridge.

      Should I use the Multirate ethernet IP?

      Kind regards,

      Nicole

    • Nicole04's avatar
      Nicole04
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Aik Eu,

      Thank you for your reply.

      I will then not use the Triple-Speed Ethernet IP for this connection.

      Should I use a transceiver or the HSIOs (with TDS) for the SGMII connection between the PHY chip and the FPGA (EMAC)?

      If I have another ethernet connection that has to be connected to the FPGA fabric (via SGMII through a transceiver), which will use the Triple-Speed Ethernet IP, can I use a shared MDIO bus between this connection and the EMAC one? Where will the MDIO signals then be connected?

      Thank you for your assistance.

      Kind regards,

      Nicole

  • aikeu's avatar
    aikeu
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Nicole04,


    Let me check with the team regarding your question.


    Thanks.

    Regards,

    Aik Eu