Agilex 5 design using DDIO shows clock routing failures

Yes, there is a HPS, but all pins used for DDIO are FPGA pins:

set_location_assignment PIN_CC19 -to a_n
set_location_assignment PIN_CF19 -to a
set_location_assignment PIN_CL6 -to b_n
set_location_assignment PIN_CK8 -to b
set_location_assignment PIN_BE50 -to c_n
set_location_assignment PIN_BF50 -to c
set_location_assignment PIN_BH41 -to d_n
set_location_assignment PIN_BH38 -to d
set_location_assignment PIN_CF22 -to q1_col_lv[3]
set_location_assignment PIN_CH22 -to q1_col_lv_n[3]
set_location_assignment PIN_CC22 -to q1_col_lv[2]
set_location_assignment PIN_CA22 -to q1_col_lv_n[2]
set_location_assignment PIN_CF28 -to q1_col_lv[1]
set_location_assignment PIN_CC28 -to q1_col_lv_n[1]
set_location_assignment PIN_CA31 -to q1_col_lv[0]
set_location_assignment PIN_CC31 -to q1_col_lv_n[0]

DDIO assignments are made with GPIO Intel FPGA IP.