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LukiLeu's avatar
LukiLeu
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 5 - LUTs

We are trying to build a TDC in an Agilex 5 FPGA by using the carry chain. We are now struggling in getting the LUTs F0-F3 configured correctly. Is it possible to use different equations for F0 and ...
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Fpga Devkit
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

This question has been addressed internally, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.