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LukiLeu's avatar
LukiLeu
Icon for New Contributor rankNew Contributor
1 year ago

Agilex 5 - LUTs

We are trying to build a TDC in an Agilex 5 FPGA by using the carry chain. We are now struggling in getting the LUTs F0-F3 configured correctly. Is it possible to use different equations for F0 and ...
Configuration
Fpga Devkit
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Have you try to compile using RTL design instead of WYSIWYG for your project? Then use the ECO method.

Since tennm_lcell_comb might not work exactly as in old legacy devices.


Regards,

Richard Tan