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MM-ATH
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11 months ago
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Agilex 5 - configure FPGA from running linux via dt-overlay

Hello, I am using HPS-first configuration scheme and I can fit FPGA from u-boot(first time it is successfull). Now I want to refit FPGA from running linux system. I am trying to follow this manual ...
  • MM-ATH's avatar
    MM-ATH
    11 months ago

    Hi all,

    finally I solved issues with help from Arrow (thank you Tomasz). The necessary things were:

    1) to modify u-boot script to exclude any accesses to fabric peripherals (eg USB reset PIO)

    echo "Trying to boot Linux from device ${target}";
    
    if test ${target} = "mmc0"; then
    
      mw.l 10d13224 14;
      mw.l 10d13228 14;
      mw.l 10d1323c 14;
      mw.l 10d13234 14;
      mw.l 10d13248 14;
      mw.l 10d1324C 14;
      mw.l 0x10D11028 0x01027fb0 1;
      mw.l 0x10c03304 0x410 1;
      mw.l 0x10c03300 0x00000410;
      mw.l 0x10c03300 0x00000000;
      mw.l 0x10c03300 0x00000410;
    
    else
        echo "mmc0 not found!"
    fi
    
    fatload mmc 0:1 ${loadaddr} ${bootfile};
    setenv bootargs "bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait";
    bootm ${loadaddr};
    
    if test ${target} = "qspi"; then
      qspi_clock=0x17d78400;
      if ubi part root; then
        ubi detach;
        mtdparts;
        ubi part root;
        ubi readvol ${loadaddr} kernel;
        ubi detach;
        setenv bootargs "earlycon panic=-1 ubi.mtd=1 root=ubi0:rootfs rootfstype=ubifs rw rootwait";
        bootm ${loadaddr};
      fi
      ubi detach;
      sf probe;
      sf read ${loadaddr} ${qspibootimageaddr} ${bootimagesize};
      setenv bootargs "earlycon root=/dev/mtdblock1 rw rootfstype=jffs2 rootwait";
      bootm ${loadaddr};
    fi
    
    if test ${target} = "nand"; then
      ubi part root;
      ubi readvol ${loadaddr} kernel;
      setenv bootargs "earlycon panic=-1 root=${nandroot} rw rootwait rootfstype=ubifs ubi.mtd=1";
      bootm ${loadaddr};
    fi

    2.) To modify and rebuild the devicetree (socfpga_agilex5_axe5_eagle.dts). Remove any references to fabric peripherals - so LEDs sections, whole soc@0 section and &usb31 section.

    overlay.dts was also simplified

    // SPDX-License-Identifier:     GPL-2.0
    /*
     * Copyright (C) 2024, Arrow Electronics, Incorporated.
     */
    
    /dts-v1/;
    /plugin/;
    
    / {
    
      fragment@0 {
        target-path = "/soc@0/base_fpga_region";
        __overlay__ {
          firmware-name = "axe5_eagle_top.hps.core.rbf";
          config-complete-timeout-us = <30000000>;
        };
      };
    };

    and now fpga_core.rbf can be (for first time) succesfully load also from linux system.